N-type field-effect transistors (NFETs) are electrically and physically isolated from other components on a semiconductor device by a shallow trench isolation (STI) layer. For example, FIG. 1 shows a conventional NFET device having a silicon layer 101 (such as a silicon substrate), an STI layer 102, and a polysilicon gate 103 disposed on silicon substrate 101 and STI layer 102. An active (i.e., channel) area 106 for the NFET channel is defined in a region of silicon substrate 101 surrounded by STI layer 102. In addition, a divot 105 at the junction between STI layer 102 and active area 106 is created as a side effect of STI layer 102 formation. This divot 105 can cause undesirable electric field concentration in the region of divot 105, thereby causing as excess current leakage due to a lowering of the threshold voltage.
To reduce these undesirable effects of divot 105, corner boron implanting has been used prior to STI filling. In this technique, the boron concentration at the active area side of divot 105 is increased by implanting boron ions using a stream 205 angled at about a twenty-degree tilt, as shown in FIG. 2(b). Boron ion stream 205 may be generated by a known boron ion stream source (not shown). As can be seen in FIG. 2(a), boron implantation is sequentially performed on each side 110, 111, 112, 113 of generally rectangular (for example, square) active area 106 by rotating the semiconductor device in ninety-degree increments and performing an intermittent boron implant for each side of active area 106. Alternatively, a continuous boron ion stream is sometimes used while the semiconductor device is continuously rotated. Boron ion stream 205 also penetrates the exposed bottom 211 of trench 210 that surrounds activate area 106 (i.e., the trench that is later filled with STI layer 102). Boron ion stream 205 is prevented from reaching the top of active area 106 by a SiN mask layer 201.
However, the above process has limitations. As semiconductor devices become increasingly smaller, the spaces between components have also become smaller, making it more difficult to effectively perform corner boron implantation. For example, referring to FIG. 2(c), when resist layer 202 is disposed over a neighboring P-type field-effect transistor (PFET) 203, the available space through which boron ion stream 205 may reach the sidewalls of active area 106 becomes quite narrow. As the space between NFET 106 and PFET 203 becomes narrower, implant shadowing (i.e., partial or even full blocking of the boron ion stream) caused by resist layer 202 becomes more of a problem. In fact, there may be a point where the space between NFET 106 and PFET 203 is so narrow that boron ion stream 205 cannot effectively reach sidewalls 110-113 at all. Others have attempted to overcome the problem of implant shadowing by forming resist layer 202 as a thinner layer. However, this makes the manufacturing process susceptible to a number of additional problems, such as having to deal with a non-uniform thickness of resist layer 202 and a smaller allowable dosage of boron implantation that may be performed (since a thinner resist layer does not mask boron ion implantation as effectively as a thicker resist layer).